Resistance capacitance (RC) delay is a significant roadblock in scaling copper interconnects beyond 14 nm technology nodes. A barrier layer is typically deposited substantially uniformly atop underlying metal and dielectric surfaces. However, barrier layer materials typically have a high k value and increase the capacitance of the interconnect resulting in RC delay.
Traditionally, thick barrier films, for example at a thickness of about 100 angstroms, have been used in order to meet etch stop, barrier and reliability parameters. However, a thick barrier film also results in an increase in overall capacitance of the interconnect. To reduce the thickness of the barrier film, a thin, high-selectivity etch stop layer (ESL), such as aluminum nitride (AlN) may be used within the interconnect. However, such thin, high-selectivity ESLs can easily be oxidized, leading to lower etch selectivity and also a degradation in reliability performance. In addition, the thinner dielectric barrier layer and the thin, high-selectivity ESL cannot act as a suitable hermetic and copper (Cu) barrier layers when deposited separately.
Accordingly, the inventors have developed improved techniques to selectively deposit dielectric barrier layers in the process of forming an interconnect and to deposit aluminum containing etch stop layers in the process of forming an interconnect.